论文标题
芯片上3D网络的功率，热和可靠性预测报告
Report on power, thermal and reliability prediction for 3D Networks-on-Chip
论文作者
论文摘要
通过将三维集成电路与芯片上的基础结构相结合，以获得芯片上的3D网络（3D-NOCS），新的片上通信范式在较低的功率，较小的足迹和较低的延迟方面带来了一些优势。但是，热耗散是3D-ICS最关键的挑战之一，在该挑战中，热量无法轻易通过几层硅传递。因此，随着平均失败时间（MTTF）随工作温度的指数降低，高温区域还面临可靠性威胁。显然，3D-NOC必须解决这个基本问题，才能被广泛使用。因此，在这项工作中，我们研究了3D-NOC的热分布和可靠性预测。我们首先提出了一种新方法，以使用现实和合成基准和标准VLSI设计流的功耗来帮助模拟温度（稳定和瞬态）。然后，基于提出的方法，我们进一步预测了网络不同部分之间的相对可靠性。实验结果表明，与加速度寿命测试相比，该方法的执行时间非常快。此外，我们比较了整体设计和基于TSV的TSV之间的热行为和可靠性。我们还可以通过一种机制来探索热量来降低工作温度的能力。
By combining Three Dimensional Integrated Circuits with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages on lower power, smaller footprint and lower latency. However, thermal dissipation is one of the most critical challenges for 3D-ICs where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature. Apparently, 3D-NoCs must tackle this fundamental problem in order to be widely used. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffics value from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based TSV. We also explorer the ability to implement the thermal via a mechanism to help reduce the operating temperature.
