论文标题
通过减少逻辑网络的乘法深度来降低量子电路的T深度
Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks
论文作者
论文摘要
逻辑网络的乘法深度$ \ {\ land，\ oplus，\ neg \} $是从主要输入到网络中主要输出的任何路径上的$ \ land $门的最大数量。我们描述了一种基于动态编程的逻辑合成算法，以减少逻辑网络中的乘法深度。它利用切割枚举，树木平衡和独家产品总和（ESOP）表示。我们的算法在密码学和量子计算中具有应用，因为乘法深度的降低直接转化为相应量子电路的较低$ t $ - 深度。我们的实验结果表明，对于AES，SHA和浮点算术的实例，与最先进的方法相比，$ t $深度的改进以及几个手工优化的量子电路的改善。
The multiplicative depth of a logic network over the gate basis $\{\land, \oplus, \neg\}$ is the largest number of $\land$ gates on any path from a primary input to a primary output in the network. We describe a dynamic programming based logic synthesis algorithm to reduce the multiplicative depth in logic networks. It makes use of cut enumeration, tree balancing, and exclusive sum-of-products (ESOP) representations. Our algorithm has applications to cryptography and quantum computing, as a reduction in the multiplicative depth directly translates to a lower $T$-depth of the corresponding quantum circuit. Our experimental results show improvements in $T$-depth over state-of-the-art methods and over several hand-optimized quantum circuits for instances of AES, SHA, and floating-point arithmetic.
