论文标题
陷阱对石墨烯晶体管静态和类似/HF性能的影响的实验观察和建模
Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors
论文作者
论文摘要
通过应用连续的栅极到源电压脉冲，在这里实验减少了陷阱引起的对石墨烯场晶体晶体管性能的滞后。该测量方案是获得可再现设备特征的实用且合适的方法。受陷阱影响和无陷阱的实验数据促进了有关陷阱对静态和动态设备性能的影响的讨论。用实验数据校准的分析流电流模型使陷阱对设备内通道电位的影响。有和没有磁滞的带有实验和合成数据获得的设备的高频数字以及从实验和合成数据获得的设备的内在增益表明，考虑陷阱对模拟和高频应用的普遍忽视影响的重要性。
The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High-frequency figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and high-frequency applications.
