论文标题
使用掺杂的硅浴缸对潜在基于良好的纳米级FDSOI MOSFET的见识 - 基于模拟和设备物理的研究：第一部分：理论和方法论
Insight into Potential Well Based Nanoscale FDSOI MOSFET Using Doped Silicon Tubs- A Simulation and Device Physics Based Study: Part I: Theory and Methodology
论文作者
论文摘要
据报道，在20 nm栅极长度下，在FDSOI MOSFET的源和排水下，具有掺杂的硅区域（浴缸）的新型平面设备。掺杂的硅区域导致在FDSOI MOSFET的源和排水区域形成潜在的井（PW），因此该设备被称为潜在的基于良好的FDSOI MOSFET（PWFDSOI MOSFET）。对PWFDSOI MOSFET的模拟和装置物理研究显示，通过数量级，设备的关闭电流降低。在20 nm栅极长度PWFDSOI MOSFET中实现了1.5 x 107的高离子/IOF f比为1.5 x 107的低IOF f比率为1.5 x 107和76 mV/dect。该研究是在具有未训练硅通道的设备上进行的。
A novel planar device having doped silicon regions (tubs) under the source and drain of an FDSOI MOSFET is reported at 20 nm gate length. The doped silicon regions result in formation of potential wells (PW) in the source and drain regions of FDSOI MOSFET and thus, the device being called as Potential Well Based FDSOI MOSFET (PWFDSOI MOSFET). Simulation and device physics study on PWFDSOI MOSFET showed reduction in the OFF current of the device by orders of magnitude. A low IOF F of 22 pA/um, high ION /IOF F ratio of 1.5 x 107 and subthreshold swing of 76 mV/decade were achieved in 20 nm gate length PWFDSOI MOSFET. The study was performed on devices with unstrained silicon channel.
