论文标题
用粗粒整体3D（M3D）集成来减轻DRAM设计的延迟区域折衷
Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration
论文作者
论文摘要
多年来，由于DRAM行业的思维方式，DRAM潜伏期并没有按比例缩放。先前的工作表明，可以通过减少DRAM访问路径的临界长度来克服这种缺点。但是，这样做会降低DRAM面积效率，加剧DRAM设计的潜伏期区域折衷。在本文中，我们表明使用新兴整体3D（M3D）集成技术重新组织DRAM细胞阵列可以减轻这些基本的潜伏区域折衷。根据我们对PARSEC基准测试的评估结果，我们设计的M3D DRAM细胞阵列组织的延迟延迟最多可减少9.56％，降低了4.96％的功耗，并且能量延迟的产品（EDP）降低了21.21％，最多可降低14％的DRAM DRAM DIE，而降低了DRAM模具，可与传统的2D DDR4 DRAM DRAM COM-PAR-PARPAR PRAM。
Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access path. However, doing so decreases DRAM area-efficiency, exacerbating the latency-area tradeoffs for DRAM design. In this paper, we show that reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D) integration technology can mitigate these fundamental latency-area tradeoffs. Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAM cell-array organizations can yield up to 9.56% less latency, up to 4.96% less power consumption, and up to 21.21% less energy-delay product (EDP), with up to 14% less DRAM die area, com-pared to the conventional 2D DDR4 DRAM.
