论文标题
偏见可估算的近序列CMOS模拟处理器，用于机器学习
Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning
论文作者
论文摘要
偏见可估算的模拟计算对于实施机器学习（ML）处理器具有不同的功能性能规格具有吸引力。例如，用于服务器工作负载的ML实现集中在更高的计算吞吐量上，以进行更快的培训，而Edge设备的ML实现则集中在节能推理上。在本文中，我们使用边缘传播原理（称为基于形状的模拟计算（S-AC））的概括来证明偏差量表近似模拟计算电路的实现。所得的S-AC核心集成了几个接近内存的计算元素，其中包括：（a）非线性激活函数； （b）内部产品计算电路； （c）混合信号压缩内存，所有这些都可以在保留其功能的同时缩放性能或功率。使用在180nm CMOS工艺中制造的原型的测量结果，我们证明了计算模块的性能对于晶体管偏置和温度的变化仍然很强。在本文中，我们还展示了偏差性和计算准确性对简单ML回归任务的影响。
Bias-scalable analog computing is attractive for implementing machine learning (ML) processors with distinct power-performance specifications. For instance, ML implementations for server workloads are focused on higher computational throughput for faster training, whereas ML implementations for edge devices are focused on energy-efficient inference. In this paper, we demonstrate the implementation of bias-scalable approximate analog computing circuits using the generalization of the margin-propagation principle called shape-based analog computing (S-AC). The resulting S-AC core integrates several near-memory compute elements, which include: (a) non-linear activation functions; (b) inner-product compute circuits; and (c) a mixed-signal compressive memory, all of which can be scaled for performance or power while preserving its functionality. Using measured results from prototypes fabricated in a 180nm CMOS process, we demonstrate that the performance of computing modules remains robust to transistor biasing and variations in temperature. In this paper, we also demonstrate the effect of bias-scalability and computational accuracy on a simple ML regression task.
