论文标题
援助：基于模拟放电的SRAM乘法加速器的准确性提高
AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator
论文作者
论文摘要
本文提出了一种新型电路（AID），以提高使用标准6T-SRAM的能源效率内存乘数的准确性。由于访问晶体管的二次性性质，基于最先进的SRAM内乘加速器在其比特线（BL，BLB）的非线性行为中遭受了非线性行为，这会导致信噪比较差（SNR）。为了在BLB电压中实现线性性，我们在访问晶体管的门上提出了一种新颖的根功能技术，与基于最先进的放电拓扑相比，平均10.77 dB SNR的准确性提高。我们的分析方法和65 nm CMOS技术中的电路模拟验证，该技术从1V的电源中消耗了每次计算的0.523 PJ（乘法，累积和预设），与其他目前的技术相比，该技术降低了51.18％。我们为4x4乘法操作进行了广泛的基于蒙特卡洛的模拟，我们的新技术对最坏情况不正确的输出方案的标准偏差小于0.086。
This paper presents a novel circuit (AID) to improve the accuracy of an energy-efficient in-memory multiplier using a standard 6T-SRAM. The state-of-the-art discharge-based in-SRAM multiplication accelerators suffer from a non-linear behavior in their bit-line (BL, BLB) due to the quadratic nature of the access transistor that leads to a poor signal-to-noise ratio (SNR). In order to achieve linearity in the BLB voltage, we propose a novel root function technique on the access transistor's gate that results in accuracy improvement of on average 10.77 dB SNR compared to state-of-the-art discharge-based topologies. Our analytical methods and a circuit simulation in a 65 nm CMOS technology verify that the proposed technique consumes 0.523 pJ per computation (multiplication, accumulation, and preset) from a power supply of 1V, which is 51.18% lower compared to other state-of-the-art techniques. We have performed an extensive Monte Carlo based simulation for a 4x4 multiplication operation, and our novel technique presents less than 0.086 standard deviations for the worst-case incorrect output scenario.
