论文标题
使用机器学习预测HLS设计结果估算的结果质量
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning
论文作者
论文摘要
机器学习（ML）已被广泛用于改善EDA工具的可预测性。使用以更高级别的抽象来表达设计的CAD工具使机器学习对于突出各种设计步骤的性能更为重要。高级合成（HLS）期间使用的行为描述是完全独立的技术，使设计人员很难解释合成选项的变化如何影响所得电路。 FPGA设计流完全采用基于HLS的方法，因此几乎没有硬件设计技能的软件工程师可以轻松使用其工具。 HLS工具允许通过修改合成选项来设计空间探索，但是，它们在HLS之后报告的结果质量（QOR）缺乏准确性。这种缺乏正确性导致了次优设计，并且在定时关闭方面存在问题。本文提出了一个强大的基于ML的设计流，可以准确预测给定行为描述后的路由后QOR，而无需合成设计。该模型是一个重要的设计探索工具，当更改本地和全球优化指令时，设计师可以快速查看对总体设计质量的影响。提出的方法具有两个强大的优势：（i）精确预测设计质量（QOR），（ii）完全消除了每个设计选项执行高级合成的需求。我们预测三个后路由参数，（i）。区域，（ii）。潜伏期和（iii）。设计的时钟周期仅通过分析高级行为代码和一些中间表示代码。我们将方法与Xilinx HLS工具集成在一起，并证明了对各种FPGA家族的准确估计。我们的估计结果在实际计算值的10 \％之内
Machine learning (ML) has been widely used to improve the predictability of EDA tools. The use of CAD tools that express designs at higher levels of abstraction makes machine learning even more important to highlight the performance of various design steps. Behavioral descriptions used during the high-level synthesis (HLS) are completely technology independent making it hard for designers to interpret how changes in the synthesis options affect the resultant circuit. FPGA design flows are completely embracing HLS based methodologies so that software engineers with almost no hardware design skills can easily use their tools. HLS tools allow design space exploration by modifying synthesis options, however, they lack accuracy in the Quality of Results (QoR) reported right after HLS. This lack of correctness results in sub-optimal designs with problems in timing closure. This paper presents a robust ML based design flow that can accurately predict post-route QoR for a given behavioral description without the need to synthesize the design. The model is an important design exploration tool where a designer can quickly view the impact on overall design quality when local and global optimization directives are changed. The proposed methodology presents two strong advantages: (i) Accurate prediction of the design quality (QoR), and (ii) complete elimination of the need to execute high-level synthesis for each design option. We predict three post route parameters, (i). Area, (ii). Latency and (iii). Clock Period of a design just by analyzing the high level behavioral code and some intermediate representation codes. We have integrated the methodology with Xilinx HLS tools and have demonstrated accurate estimation on a variety of FPGA families. Our estimated results are within 10\% of actual computed values
