论文标题
通过使用细硅量子井来减少量子点中的电荷噪声
Reducing charge noise in quantum dots by using thin silicon quantum wells
论文作者
论文摘要
宿主半导体中的电荷噪声降低了自旋质量的性能，并为控制大量子处理器的障碍物构成了障碍。但是，要设计栅极定义的量子点的异质材料堆栈，以系统地改善电荷噪声，这是一项挑战。在这里，我们讨论了半导体 - 二元界面和$^{28} $ si/sige异质结构的埋入量子孔，并显示电荷噪声之间的连接，在量子点上以量子点进行测量，在宿主半导体中测量了用宏观霍尔杆测量的宿主半导体。在5 nm厚的$^{28} $ si量子井中，我们发现，在100 mm晶圆上的二维电子气体的散射特性和均匀性的改善对应于充电噪声的显着减少，最低值为0.29 $ \ pm $ 0.02 $ 0.02 $ $ 0.02 $ $ $ EV/SQRT（HZ）（Hz），在1 Hz At vast vast vaste vasted and vastevess vots vest vots vots and vasted vots vots vots vots avers vots。我们将测得的电荷噪声推送到模拟的dephasing时间到CZ-GATE的保真度，以提高近一个数量级。这些结果表明，清洁，安静的结晶环境将长寿和高保真的自旋量子集成到更大的系统中。
Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a $^{28}$Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick $^{28}$Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29$\pm$0.02 $μ$eV/sqrt(Hz) at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to cz-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.
