论文标题
AMD罗马记忆障碍
The AMD Rome Memory Barrier
论文作者
论文摘要
随着AMD作为CPU行业竞争对手的迅速增长，必须进行高性能和建筑工程师分析新的AMD CPU。通过了解新的和陌生的体系结构，工程师可以使其算法充分利用新硬件。此外，工程师能够预测架构的局限性，并确定何时需要特定工作量的替代平台。本文提出的结果表明，一旦应用程序的存储器带宽超过37.5 GIB/S，用于整数较重的应用程序或用于浮动点重点工作量的100 GIB/s，就会受到AMD“ Rome”体系结构的性能。出现了记忆带宽和CPI之间的强正相关性，以及增加的内存负载与从规格CPU2017基准套件的基准的时间完成之间的强正相关。
With the rapid growth of AMD as a competitor in the CPU industry, it is imperative that high-performance and architectural engineers analyze new AMD CPUs. By understanding new and unfamiliar architectures, engineers are able to adapt their algorithms to fully utilize new hardware. Furthermore, engineers are able to anticipate the limitations of an architecture and determine when an alternate platform is desirable for a particular workload. This paper presents results which show that the AMD "Rome" architecture performance suffers once an application's memory bandwidth exceeds 37.5 GiB/s for integer-heavy applications, or 100 GiB/s for floating-point-heavy workloads. Strong positive correlations between memory bandwidth and CPI are presented, as well as strong positive correlations between increased memory load and time-to-completion of benchmarks from the SPEC CPU2017 benchmark suites.
