论文标题
三元阈值逻辑门的实现和应用
Implementation and Applications of a Ternary Threshold Logic Gate
论文作者
论文摘要
减少逻辑电路的延迟，功耗和芯片区域是设计师的主要目标。在大多数情况下，设计师牺牲了功耗和芯片区域，以改善给定技术节点的延迟。为了克服这个问题，我们提出了一个三元阈值逻辑门。我们通过组合阈值逻辑和三元逻辑来实现所提出的门。然后，我们使用所提出的门构建了三元Alu（作为逻辑门，比较器和算术电路）的基本构建块。我们表明，拟议的三元TLG通过模拟改善了三元电路的延迟，功耗和芯片区域。因此，所提出的门可用于改善三元电路的延迟，功耗和芯片面积。
Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node. To overcome this problem, we propose a ternary threshold logic gate. We implement the proposed gate by combining threshold logic and ternary logic. Then, we construct basic building blocks of a ternary ALU (as logic gates, comparator, and arithmetic circuits) using the proposed gate. We show that the proposed ternary TLG improves delay, power consumption, and chip area of ternary circuits via simulations. Thus, the proposed gate can be used to improve delay, power consumption, and chip area of ternary circuits.
